As circuit density continues to increase, there is a corresponding drive to produce smaller and smaller field effect transistors. Field effect transistors have typically been formed by providing active areas within a bulk substrate material or within a complementary conductivity type well formed within a bulk substrate. Although the field effect transistor feature size is reducing with advances in process technology, even smaller transistors can be formed from thin films deposited over oxide. These transistors are commonly referred to as "thin film transistors" (TFT).
With TFTs, a thin film of semiconductive material is first provided. A central channel region of the thin film is masked, while opposing adjacent source/drain regions are doped with an appropriate p or n type conductivity enhancing impurity. A gate insulator and gate are provided either above or below the thin film channel region, thus providing a field effect transistor having an active channel region formed entirely within a thin film as opposed to a bulk substrate.
The invention grew out of needs associated with TFTs and their usage in high-density static random access memories (SRAMs). A static memory cell is characterized by operation in one of two mutually exclusive and cell-maintaining operating states. Each operating state defines one of the two possible binary bit values, 0 or 1. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a "high" voltage to indicate a "set" operating state. The memory cell output produces a "low" voltage to indicate a "reset" memory cell operating state. A low or reset output voltage usually represents a binary value of 0, and a high or set output voltage represents a binary value of 1 .
A static memory cell is said to be bi-stable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to operating states of the memory cell, as long as the memory cell receives power.
The operation of the static memory cell is in contrast to other types of memory cells, such as dynamic cells, which do not have stable operating states. A dynamic memory cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or "refreshing" to maintain this voltage for more than very short time periods. A dynamic memory cell has no feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift towards intermediate or indeterminate voltages, effectively resulting in loss of data.
Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, rather than the six transistors typically required in a static memory cell. SRAM cell density is maximized with three-dimensional integration. For example, load transistors of the SRAM cell constitute TFTs which are folded over the bulk transistors. Because of the significantly different architectural arrangements and functional requirements of static and dynamic memory cells and circuits, static memory design has developed along a different path than has the design of dynamic memories.
Ongoing efforts in SRAM circuitry have brought about the development of TFTs in an attempt to minimize space and for other advantageous regions associated with TFTs. While the invention grew out of needs associated with TFTs of SRAM circuitry, the artisan will appreciate applicability of the invention to other types of circuitry.
One common material utilized as the thin source, channel and drain film in a TFT is polysilicon. Such is comprised of multiple forms of individual single crystal silicon grains. The locations where two individual crystalline grains abut one another is commonly referred to as a grain boundary. Grain boundaries are inherent in polycrystalline materials, such as polysilicon, as it is the boundaries which define the breaks between individual crystal grains. The crystalline structure breaks down at the grain boundaries, giving rise to a high concentration of broken or "dangling" Si bonds. These dangling bonds "trap" carriers and give rise to potential barriers at the grain boundaries. These potential barriers impede the flow of carriers in polysilicon, thus reducing conductivity.
The grain boundary potential barrier height is proportional to the square of the dangling bond density, or "trap density". The smaller the grain size, the higher the trap density and thus the lower the conductance. In a TFT, the grain boundary potential barrier height is controlled by the gate voltage, and hence the conductivity is a function of the gate voltage. A larger trap concentration makes it harder for the gate to form a channel resulting in a higher threshold voltage and a lower drive current.
The grain boundary trap concentration also affects the leakage current in TFTs. In polysilicon or other polycrystalline TFTs, the presence of grain boundary traps at the drain end can dramatically increase the leakage current in the presence of a "gate-to-drain" electric field. The increase in leakage results from either "thermionic field emission" and/or "Poole-Frenkel" emission through the grain boundary traps. Accordingly, the greater the number of grain boundaries (i.e., the smaller the grain size), the greater the current leakage through the material. Greater current leakage means that more power is required to replace the leaking current to maintain an SRAM cell transistor in its desired powered-on state. Such leakage is particularly adverse in laptop computers, where desired power consumption when a cell's state is not being changed would be desired to be very low to extend battery life.
High density SRAMs (16 Mb or higher) typically require TFTs with low OFF currents (&lt;50fA) and high ON current (&gt;5nA) in order to obtain acceptable low standby leakage and high memory cell stability. Current state-of-the-art TFTs provide low standby current at the expense of ON current, or at the expense of additional process complexity. One present way of minimizing this current leakage at the cost of increased process complexity is by providing a "lightly doped offset" (LDO) region within the thin film. A lightly doped offset region is an elongated region within the thin film which is positioned effectively between the channel region and the drain region. Such a region provides a buffer zone for the electric field between the channel and drain which minimizes leakage therebetween.
It would be desirable to improve upon prior art thin film transistor constructions in a manner which further minimizes leakage current.